Projects using SpinalHDL
------------------------

Note that the following lists are very incomplete.

.. _users_repositories:

Repositories
^^^^^^^^^^^^

* `J1Sc Stack CPU <https://github.com/SteffenReith/J1Sc>`_
* `VexRiscv CPU and SoC <https://github.com/SpinalHDL/VexRiscv>`_
* `NaxRiscv CPU <https://github.com/SpinalHDL/NaxRiscv>`_
* `SaxonSoc <https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/digilent/ArtyA7SmpLinux>`_
* `VexiiRiscv CPU <https://github.com/SpinalHDL/VexiiRiscv>`_
* `open-rdma <https://github.com/datenlord/open-rdma>`_
* `MicroRV32 SoC <https://github.com/agra-uni-bremen/microrv32>`_
* \.\.\.


Companies
^^^^^^^^^

* `DatenLord, China <https://datenlord.github.io/>`_

    * `RoCE v2 hardware implementation <https://github.com/datenlord/open-rdma>`_
    * `WaveBPF <https://github.com/datenlord/wavebpf>`_ (wBPF): a
      "tightly-coupled multi-core" eBPF CPU, designed to be a high-throughput
      coprocessor for processing in-memory data (e.g. network packets).

* `Elitestek (FPGA Vendor), China <https://elitestek.com/product/RISC_V/>`_

    "Elitestek has used the VexRISC-V core in FPGAs and applied in multi
    applications in worldwide customers."

* `LeafLabs, Massachusetts, USA <https://www.leaflabs.com>`_

    `SpinalHDL To Accelerate Neuroscience (PDF slideshow)
    <https://github.com/SpinalHDL/SpinalHDL/files/10219043/SpinalHDL.To.Accelerate.Neuro.pdf>`_

* QsPin, Belgium

* `Tiempo Secure, France <https://www.tiempo-secure.com/>`_

    `SpinalHDL for ASIC (PDF slideshow)
    <https://github.com/SpinalHDL/SpinalHDL/files/10239051/SpinalHDL.for.ASIC.pdf>`_
* \.\.\.

Universities
^^^^^^^^^^^^

* `Universität Bremen - Fachbereich 3 - Informatik, Germany
  <http://www.informatik.uni-bremen.de/agra/ger/index.php>`_

    `SpinalHDL in Computer Architecture Research and Education (PDF slideshow)
    <https://github.com/SpinalHDL/SpinalHDL/files/10244833/20221216_summit_saahm.pdf>`_

* `Universität Potsdam - Embedded Systems Architectures for Signalprocessing,
  Germany <https://www.uni-potsdam.de/en/aess/>`_

    `A Network Attached Deep Learning Accelerator for FPGA Clusters (PDF
    slideshow)
    <https://github.com/SpinalHDL/SpinalHDL/files/10238707/A_Network_Attached_Deep_Learning_Accelerator_for_FPGA_Clusters.pdf>`_
* \.\.\.